1. Field of the Invention
The present invention relates to a thin film transistor and fabricating method thereof. More particularly, the present invention relates to a thin film transistor and fabricating method thereof with fewer photolithography steps.
2. Description of the Related Art
Thin film transistors (TFTs) drive pixels in active matrix type liquid crystal display devices, active matrix type organic light-emitting display devices, image sensors and the like. Generally, TFTs used in these apparatuses are formed from silicon semiconductor thin film. Such silicon semiconductor thin films are roughly classified into two types: amorphous silicon (a-Si) semiconductor and crystalline silicon semiconductor films.
The crystalline silicon TFT is advantageous in that the surface of a crystalline silicon layer has a fewer defects than that of the amorphous silicon, thus the crystalline silicon TFT has a higher mobility. Currently crystalline silicon TFT is being substituted for amorphous silicon TFT in the fabrication of precise elements and pixel arrays. Compared to the number of process steps required to form an amorphous silicon TFT, however, more process steps are required to form crystalline silicon TFT hence, the process is more complicated and time-consuming.
FIGS. 1a to 1h are cross sections of the manufacturing process of a conventional complementary metal-oxide semiconductor. First, referring to FIG. 1a, a substrate 10 with a buffer layer 11 and an amorphous silicon layer 12 thereon is provided. Then the amorphous silicon layer 12 is crystallized to form a crystalline silicon layer 13, and the crystalline silicon layer 13 is patterned by photolithography to form silicon islands 13n and 13p, as shown in FIG. 1b. 
Referring to FIG. 1c, an insulating film 15 and a conductive layer 16 are formed on the buffer layer 11 and silicon islands 13n and 13p, and the conductive layer 16 formed on the silicon island 13p of a p-type transistor is patterned by photolithography to serve as a gate electrode 16p. Furthermore, a mask layer 20 and the gate electrode 16p are used as masks to form a p+ poly-silicon region 18p by p-type ion implantation of the silicon island 13p. 
FIG. 1d shows the formation of a patterned resist layer 22 on the p-type transistor and prescribed parts of the conductive layer 16 located on the silicon island 13n for an n-type transistor. Next, the exposed conductive layer 16 is etched to form a gate electrode 16n of the n-type transistor. Then, the silicon island 13n is implanted with n-type ion to form an n+ poly-silicon region 18n, with the gate electrode 16n and the resist layer 22 acting as masks.
FIG. 1e shows the removal of part of the resist layer 22 located on the gate electrode 16n to form a resist layer 22a by isotropic etching. The gate electrode 16n is then etched to form a gate electrode 16n′, with the resist layer 22a acting as a mask. The gate electrode 16n′ and the resist layer 22a are then used as masks to form an n− poly-silicon region 28 by n-type ion implantation.
Referring next to FIG. 1f, the resist layer 22a is removed. A first silicon oxide layer 30 is then formed on the above structure and etched to form contact holes 30a by photolithography. Then, referring to FIG. 1g, signal lines 35 is formed into the contact holes, wherein the single line 35 is constructed of a first metal layer 31 and a second metal layer 32 patterned in a prescribed shape by photolithography.
Subsequently, referring to FIG. 1h, a second silicon oxide layer 40 is formed to act as a protective film. The second silicon oxide layer 40a is then etched to form a contact hole 40a in a region located over the signal line of the N-type thin film transistor by photolithography. Finally, a transparent conductive film constituting the contact hole 40a and a pixel electrode 50 is formed and patterned to provide a crystalline silicon TFT.
The conventional fabrication method described above requires nine photolithography steps, which increases costs and lowers throughput and yield.
Seeking to solve the previously described problem, a crystalline silicon TFT manufacturing process requiring fewer photolithography steps is disclosed. FIGS. 2a to 2e are schematic views showing the crystalline silicon TFT manufacturing process with fewer photolithography steps. First, referring to FIG. 2a, a substrate 100 with a first conductive layer thereon is provided. Next, the first conductive layer is etched to form a source electrode 101 and a drain electrode 103. A first insulating layer 102, an amorphous silicon layer 104, and a gate oxide layer 106 are then formed sequentially on the conductive layer.
FIG. 2b shows the conversion of the amorphous silicon layer 104 into a crystalline silicon layer 108 by crystallization. Next, using a photolithography and etching technique, the crystalline silicon layer 108 and the gate oxide layer 106 are patterned to prescribed forms.
Then, a second conductive layer is deposited on the gate oxide layer 106. Next, the second conductive layer and the gate oxide layer 106 are simultaneously etched to respectively form a gate electrode 120 and a gate oxide layer 106′ by photolithography. Next, the crystalline silicon layer 108 is doped with impurity ions using the gate electrode 120 as a mask to define a drain region 123 and a source region 121, as shown in FIG. 2c. 
A second insulating layer 112 comprising SiO2 is then formed to cover the above. Next, the second insulating layer 112 is patterned to form a source region contact hole 131, a drain region contact hole 133, a source electrode contact hole 141, and a drain electrode contact hole 143 by photolithography, as shown in FIG. 2d. Finally, a first connecting electrode 151 connects the source electrode 101 to the source region 121 via the contact holes 141 and 131 and a second connecting electrode 153 connecting the drain electrode 103 to the drain region 123 via the contact holes 143 and 133 are formed, as shown in FIG. 2e. 
The fabrication method of the present requires fewer photolithography steps. It is, however, critical to form the source region contact hole 131 and the source electrode contact hole 141 (or the drain region contact hole 133 and the drain electrode contact hole 143) simultaneously. The opening of each contact hole, however, is at a different height and etching the uneven surface is difficult. The source region contact hole 131 is formed by etching through the second insulating layer 112 and the source electrode contact hole 141 is formed by etching through the first insulating layer 102 and the second insulating layer 112, and the depth ratio between the first insulating layer and second insulating layer is typically 1:1.
That is, the narrow process window of the conventional crystalline silicon TFT increases the difficulty of manufacturing. Additionally, the crystallization process window is limited as a result of the metal lines formed prior to crystallization.
Another conventional crystalline silicon TFT manufacturing process reduces the number of photolithography steps by taper etching. However, the process window of this manufacturing process is also limited due to the harsher requirements of tape angles of the source/drain electrodes and complicated crystallization.
Therefore, on the premise that the process window is unlimited and the process complexity is not increased, a crystalline silicon TFT manufacturing process with fewer photolithography steps than the conventional method to decrease manufacturing costs is called for.